The present inventions relate generally to data processing systems, and more specifically, to data processing systems having a capability to plan hardware-accelerated functional verification of a circuit design.
Functional verification is the task of verifying that a logic design conforms to a specification. Functional verification may include simulating the logic design of an integrated circuit using software-based simulators that are facilitated by hardware accelerators. Hardware accelerators are special-purpose machines that can increase performance by several orders of magnitude, reducing otherwise month-long simulations to days or even hours. The hardware accelerators are programmed by loading its memory with an instruction stream produced prior to simulation by a compiler that schedules each logical primitive at a specific time on a specific processor.